The present invention concerns an apparatus, method and system for counting logic events, determining logic event histograms and for identifying a logic event in a logic arrangement or environment.
For system performance tuning, it is believed that the capability to measure particular characteristics, such as various performance characteristics, of a processor platform or system facilitates the ability to xe2x80x9ctunexe2x80x9d such systems to determine where improvements may be made. Types of instrumentation approaches that may be used to measure various system characteristics may include counter-based instrumentation and trace-based instrumentation.
The trace-based instrumentation approach may use external hardware to probe a system to collect and store long operating xe2x80x9ctracesxe2x80x9d. Such trace-based instrumentation may include some arrangement or structure for post-processing the collected traces to provide certain data, including charts. While relatively complex metrics (such as, for example, distributions across certain operating conditions) may be gathered using trace-based instrumentation rather than counter-based instrumentation, trace-based instrumentation may be relatively expensive. Thus, for example, a relatively large memory may be required to store the collected traces if the experiment is a xe2x80x9clongxe2x80x9d one. Also, some of the system signals may be physically inaccessible to external hardware.
While a logic analyzer trace approach may be used to provide histogramming or single event measurements, such tracing may be limited to collecting measurement statistics based on externally available signals. Such an approach may, for example, provide relatively limited sampling of only a relatively small subset of the total xe2x80x9ctrafficxe2x80x9d on a bus as trace memory fills quickly and empties slowly. Further, higher speed point-to-point busses may make the logic analyzer tracing approach more difficult or impractical. Also, validating the performance of, for example, a bus interface requires measuring throughputs and latencies. Although this may be done with logic analyzers that may be coupled to busses driven by exerciser cards, this may be relatively expensive, difficult and/or time-consuming.
The counter-based instrumentation approach may use a counter to count a number of events occurring over some sample period. Such counter-based instrumentation may be included on some integrated circuit devices so that data may be collected from internal signals. This approach may determine average metrics, such as throughput, using the counter. One counter-based circuit arrangement is described in U.S. Pat. No. 6,018,803, which issued on Jan. 25, 2000 and which is assigned to Intel Corp. Additionally, U.S. Pat. No. 6,026,139, which issued on Feb. 15, 2000 and which is assigned to Intel Corp., describes an integrated counter-based instrumentation for generating a frequency distribution or histogram. While histograms of, for example, bus latencies and burst sizes may be important, it is believed that at least for some types of workloads (such as, for example, real-time workloads), identifying certain single events may also be important.
In this regard, deficient or faulty system components within a system may damage system performance in ways that may be difficult to find or identify. Thus, for example, if graphics cards do not accept write-data from the processor for relatively long periods of time (such as milliseconds), this may, for example, cause video or audio glitches. At present, such a problem may be addressed with relatively great difficulty and/or expense by developing a specialized peripheral component interface card that may be used to aid in finding such events.
Accordingly, it is believed that there is a need for an instrumentation architecture, apparatus, method and system that is capable of counting or measuring logic event parameters, collecting or determining histogram information of various metric values, such as, for example, performance characterizing parameters, and identifying single logic events that may affect performance so as to better allow any one or more of the above desired results.
Additionally, estimating application runtimes for proposed system hardware and/or software configuration changes may be problematic. While, for example, a processor bus first word latency metric may indicate system performance at some level, it may only be sufficient under certain limited conditions.
Accordingly, it is believed that there is a need for an apparatus, method and system for determining estimated application runtimes based on histogram or distribution information.